The present invention relates generally to the manufacture of integrated resistor networks. More particularly, the present invention relates to an integrated resistor network that advantageously minimizes the cross talk between and among its various components.
Cross talk represents the unwanted interference experienced by a signal due to the presence of another signal in another part of the circuit. In the past, integrated resistor networks, i.e., those implemented on a semiconductor wafer die, have suffered from a high level of cross talk between adjacent resistors due to their high level of parasitic capacitance and inductance. These parasitic capacitances and inductances exist in the common and adjacent conductors that couple together the resistors, as well as in those that couple individual resistors to their respective pins. Due to the cross talk, the signal on one conductor is affected when another signal is present on another conductor on the semiconductor wafer die. When there is cross talk, the affected signal may be altered, giving rise to errors. In general, the higher the frequency at which the resistor network is operated, the more susceptible to cross talk it becomes.
FIG. 1A illustrates a representative prior art integrated resistor network to facilitate discussion of the cross talk problem. An equivalent circuit for the prior art resistor network of FIG. 1A is shown in a subsequent drawing FIG. 1B. Referring now to FIG. 1A, there is shown a wafer die 100, on which an integrated resistor network comprising resistors R1-R22 are implemented. Each of resistors R1-R22 is coupled to a common surface bus 102 via surface feeder conductors 104. As shown, there is at least one surface feeder conductor 104 from each resistor to common surface bus 102. Each of resistors R1-R22 is further coupled to one of respective pads P1-P22 via another surface conductor.
In operation, the coupling of adjacent resistors via their respective feeder conductors 104 and common surface bus 102 gives rise to inductance. This inductance in turn increases the susceptibility of signals on adjacent pins (and concomitantly on adjacent resistors) to cross talk. Such inductance between adjacent pins through common surface bus 102 is represented, for example, by inductors 202 in the circuit equivalence drawing of FIG. 1B.
Further, since the common node of the resistors, i.e., common surface bus 102, resides strictly at the top surface of the die in the prior art, it is necessary to couple common contact conductors from the common contact pads, e.g., pads 106 and 108, of the die to common surface bus 102 to provide an electrical path thereto. In FIG. 1A, these common contact conductors are designated by reference numerals 105 and 107. The presence of common contact conductors 105 and 107 gives rise to additional inductance, which is representatively identified in FIG. 1B by inductors 204. As can be appreciated, the presence of parasitic inductors 202 and 204 through the common resistor node contributes to the high level of cross talk between adjacent resistors of the prior art integrated resistor network.
Additionally, the prior art resistor network of FIG. 1A implements their resistors on top of a floating substrate of semiconductor wafer die 100. This floating substrate, which underlies the resistors, gives rise to capacitive coupling among the resistors. The resulting capacitors that are formed between the floating substrate and the resistive regions of the resistors as well as between the floating substrate and the resistors' pads are shown representatively by capacitors 206 and 208 respectively in FIG. 1B. Because of this capacitive coupling, whenever there is a potential level on a given resistor, this voltage potential will affect, via the floating substrate, signals at other parts of the wafer die. The result is an elevated level of cross talk among the resistors of the prior art integrated resistor network.
In view of the above, what is desired is improved methods and apparatus for forming integrated resistor networks. The improved integrated resistor network preferably offers improved electrical characteristics, particularly at high frequencies, by reducing the parasitic inductance and capacitance between and among the resistors of the integrated resistor network.